Jason Matalka

About

I have over 15 years of experience developing embedded systems for high-reliability applications. I’ve spent the last 4 years developing embedded firmware and FPGA gateware for remote / autonomous automotive systems. I have an additional 9 years of experience developing mission-critical embedded systems with organizations such as NASA, CERN, and the US NAVY. As a design engineer at smaller companies and start-ups, I’ve been responsible for the design and bring-up for a variety of embedded systems. I’ve worked directly with government and private sector customers to establish and refine project requirements, performed on-site testing, and hosted demonstrations and given technical presentations.

Experience

• Senior Embedded Engineer · Vay Technology, GmbH.03-01-2020

  ● Lead developer of ISO26262 ASIL gateware on Lattice XP2 FPGA in VHDL. ● Created validation tests in Questa / ModelSim utilizing VHDL-2008 and System Verilog. ● Collaborated on system architecture design for a remote / autonomous driving platform that monitors vehicle performance, verifies system integrity, and controls fail-safe / fail-operational behaviors. ● Developed firmware in Embedded C for Infineon Aurix TriCore multi-core processor running PX-ROS. ● Coordinated MCU, RTOS, and development software selection, hardware bring-up, and performance debugging. ● Worked closely with Hardware Design and Embedded Development teams to establish system requirements, safety analysis, and test/validation requirements. ● Managed automated build / test / release pipelines in CircleCI, GitHub, AWS ECR & S3.

• Lead Firmware Engineer · Polysync Technology10-01-2019 – 03-01-2020

  ● Lead firmware development for ISO26262 remote driving system based on TI Hercules (ARM-R4F) processor. ● Coordinated development efforts between MCU, FPGA, Safety, Hardware, & Test teams. ● Programmed application code extensively in Embedded Rust running in Safe-RTOS environment.

• Senior Embedded Software Engineer · Phoseon, Inc.08-01-2017 – 10-01-2019

  ● Developed gateware in for Microsemi FPGAs (VHDL) for 1Msps data sampling and filtering ● Authored Embedded C firmware on a variety of microprocessors including ARM Cortex-M4 & TI DSPs. ● Utilized Free-RTOS for scheduling, data processing, and system performance monitoring. ● Implemented real-time processing and noise reduction filters in software using wavelet algorithms. ● Debugged a variety of hardware issues using oscilloscopes, logic analyzers, JTAG debuggers, etc.

• Senior Design Engineer · Invocon, Inc.01-01-2009 – 08-01-2017

  ● Designed high-reliability embedded systems to meet NASA and MIL requirements. ● Authored FPGA & CPLD code in VHDL for several high-speed telemetry and data acquisition systems. ● Worked extensively with Actel / Microsemi and Xilinx FPGAs. ● Developed firmware in C for embedded systems utilizing TI DSPs and MCUs. ● Conducted research and development of low-power embedded systems utilizing Li-Ion rechargeable cells. ● Experience with system utilizing a variety of protocols: USB, I2C, SPI, Ethernet, RS-232/422/485, & Bluetooth ● Automated product verification testing using Python/Perl scripts to control GPIB test equipment. ● Performed schematic design using Altium for mission-critical hardware. ● Worked with clients to establish specifications, conducted project presentations, and authored technical documentation.

• x86 Architectural Verification Engineer · Centaur Technology08-01-2006 – 06-01-2008

  ● Generated x86 assembly code (ASM) tests for functional verification of processor features. ● Analyzed x86 processor Verilog and micro-code to determine the root cause of test failures. ● Maintained 800 machine server cluster for random test generation and RTL model simulations.

• System Debug & Product Test/Development Co-op Engineer · Advanced Micro Devices (AMD)09-01-2001 – 08-01-2004

  ● Received “Outstanding Contributions Award” for discovering critical chipset bugs. ● Used hardware and software In Circuit Emulators (ICE) for exploring x86 ASM code flow. ● Utilized logic analyzer for debugging 1GHz+ DDR, Hyper Transport, PCI, and AGP bus issues.

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